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dual very low noise precision operational amplifier data sheet op270 rev. f document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2001C2015 analog devices, inc. all rights reserved. technical support www.analog.com features very low noise density of 5 nv/hz at 1 khz maximum excellent input offset voltage of 75 v maximum low offset voltage drift of 1 v/c maximum very high gain of 1500 v/mv minimum outstanding cmr of 106 db minimum slew rate of 2.4 v/s typical gain bandwidth product of 5 mhz typical industry-standard 8-lead dual pinout functional block diagrams 00325-001 ?in a 1 +in a 2 nc 3 v? 4 out a 16 nc 15 nc 14 v+ 13 nc 5 nc 12 +in b 6 nc 11 ?in b 7 out b 10 nc 8 nc 9 nc = no connect op270 figure 1. 16-lead soic (s-suffix) 00325-002 op270 out a ab 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 figure 2. 8-lead pdip (p-suffix) 8-lead cerdip (z-suffix) general description the op270 is a high performance, monolithic, dual operational amplifier with exceptionally low voltage noise density (5 nv/hz maximum at 1 khz). it offers comparable performance to the industry-standard op27 from analog devices, inc. the op270 features an input offset voltage of less than 75 v and an offset drift of less than 1 v/c, guaranteed over the full military temperature range. open-loop gain of the op270 is more than 1,500,000 into a 10 k load, ensuring excellent gain accuracy and linearity, even in high gain applications. the input bias current is less than 20 na, which reduces errors due to signal source resistance. with a common-mode rejection (cmr) of greater than 106 db and a power supply rejection ratio (psrr) of less than 3.2 v/v, the op270 significantly reduces errors due to ground noise and power supply fluctuations. the power consumption of the dual op270 is one-third less than two op27 devices, a significant advantage for power conscious applications. the op270 is unity-gain stable with a gain bandwidth product of 5 mhz and a slew rate of 2.4 v/s. the op270 offers excellent amplifier matching, which is important for applications such as multiple gain blocks, low noise instrumentation amplifiers, dual buffers, and low noise active filters. the op270 conforms to the industry-standard 8-lead cerdip and pdip pinouts. for higher speed applications, the ada4004-2 or the ad8676 are recommended. for a quad op amp, see the op470 data sheet.
op270* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. documentation application notes ? an-649: using the analog devices active filter design tool ? an-940: low noise amplifier selection guide for optimal noise performance data sheet ? op270: dual very low noise precision operational amplifier data sheet tools and simulations ? op270 spice macro model design resources ? op270 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all op270 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
op270 data sheet rev. f | page 2 of 20 table of contents features .............................................................................................. 1 ? functional block diagrams ............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical specifications ............................................................... 4 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? typical performance characteristics ............................................. 6 ? test circuits ..................................................................................... 11 ? applications information .............................................................. 12 ? voltage and current noise ........................................................ 12 ? total noise and source resistance ........................................... 12 ? noise measurements .................................................................. 14 ? capacitive load driving and power supply considerations .... 15 ? unity-gain buffer applications ............................................... 15 ? low phase error amplifier ....................................................... 16 ? five-band, low noise, stereo graphic equalizer .................. 16 ? digital panning control ............................................................ 17 ? dual programmable gain amplifier ....................................... 17 ? outline dimensions ....................................................................... 19 ? ordering guide .......................................................................... 20 ? revision history 10/15rev. e to rev. f changes to general description section ...................................... 1 changes to supply voltage parameter and differential input voltage parameter, table 3 .............................................................. 5 deleted table 4; renumbered sequentially .................................. 5 2/10rev. d to rev. e change to input noise current density parameter, table 1 ...... 3 change to figure 18 ......................................................................... 8 2/09rev. c to rev. d updated format .................................................................. universal reorganized layout ............................................................ universal changes to figure 7 .......................................................................... 6 changes to figure 22 ........................................................................ 9 deleted applications heading ...................................................... 11 changes to figure 44 ...................................................................... 17 changes to figure 46 ...................................................................... 18 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 4/03rev. b to rev. c deletion of op270a model ............................................... universal edits to features ................................................................................. 1 changes to specifications ................................................................. 2 deletion of wafer limits and dice characteristics ...................... 4 changes to absolute maximum ratings ........................................ 4 changes to ordering guide ............................................................. 4 changes to equations in noise measurements section ............. 10 change to figure 10 ....................................................................... 11 updated outline dimensions ....................................................... 14 11/02rev. a to rev. b updated ordering guide .............................................................. 15 9/02rev. 0 to rev. a edits to absolute maximum ratings .............................................. 5 edits to ordering guide ................................................................ 15 2/01revision 0: initial version
data sheet op270 rev. f | page 3 of 20 specifications v s = 15 v, t a = 25c, unless otherwise noted. table 1. parameter symbol test conditions op270e op270f op270g unit min typ max min typ max min typ max input offset voltage v os 10 75 20 150 50 250 v input offset current i os v cm = 0 v 1 10 3 15 5 20 na input bias current i b v cm = 0 v 5 20 10 40 15 60 na input noise voltage 1 e n p-p 0.1 hz to 10 hz 80 200 80 200 80 nv p-p input noise voltage density 2 e n f o = 10 hz 3.6 6.5 3.6 6.5 3.6 nv/hz e n f o = 100 hz 3.2 5.5 3.2 5.5 3.2 nv/hz e n f o = 1 khz 3.2 5.0 3.2 5.0 3.2 nv/hz input noise current density i n f o = 10 hz 1.1 1.1 1.1 pa/hz i n f o = 100 hz 0.7 0.7 0.7 pa/hz i n f o = 1 khz 0.6 0.6 0.6 pa/hz large-signal voltage gain a vo v o = 10 v, r l = 10 k 1500 2300 1000 1700 750 1500 v/mv v o = 10 v, r l = 2 k 750 1200 500 900 350 700 v/mv input voltage range 3 ivr 12 12.5 12 12.5 12 12.5 v output voltage swing v o r l 2 k 12 13.5 12 13.5 12 13.5 v common-mode rejection cmr v cm = 11 v 106 125 100 120 90 110 db power supply rejection ratio psrr v s = 4.5 v to 18 v 0.56 3.2 1.0 5.6 1.5 5.6 v/v slew rate sr 1.7 2.4 1.7 2.4 1.7 2.4 v/s supply current (all amplifiers) i sy no load 4 6.5 4 6.5 4 6.5 ma gain bandwidth product gbp 5 5 5 mhz channel separation 1 cs v o = 20 v p-p, f o = 10 hz 125 175 125 175 175 db input capacitance c in 3 3 3 pf input resistance differential mode r in 0.4 0.4 0.4 m common mode r incm 20 20 20 g settling time t s a v = +1, 10 v, step to 0.01% 5 5 5 s 1 guaranteed but not 100% tested. 2 sample tested. 3 guaranteed by cmr test.
op270 data sheet rev. f | page 4 of 20 electrical specifications v s = 15 v, ?40c t a 85c, unless otherwise noted. table 2. parameter symbol test conditions op270e op270f op270g unit min typ max min typ max min typ max input offset voltage v os 25 150 45 275 100 400 v average input offset voltage drift tcv os 0.2 1 0.4 2 0.7 3 v/c input offset current i os v cm = 0 v 1.5 30 5 40 15 50 na input bias voltage i b v cm = 0 v 6 60 15 70 19 80 na large-signal voltage gain a vo v o = 10 v, r l = 10 k 1000 1800 600 1400 400 1250 v/mv a vo v o = 10 v, r l = 2 k 500 900 300 700 225 670 v/mv input voltage range 1 ivr 12 12.5 12 12.5 12 12.5 v output voltage swing v o r l 2 k 12 13.5 12 13.5 12 13.5 v common-mode rejection cmr v cm = 11 v 100 120 94 115 90 100 db power supply rejection ratio psrr v s = 4.5 v to 18 v 0.7 5.6 1.8 10 2.0 1.5 v/v supply current (all amplifiers) i sy no load 4.4 7.2 4.4 7.2 4.4 7.2 ma 1 guaranteed by cmr test.
data sheet op270 rev. f | page 5 of 20 absolute maximum ratings table 3. parameter rating supply voltage 18 v differential input voltage 1 1.0 v differential input current 1 25 ma input voltage supply voltage output short-circuit duration continuous storage temperature range ?65c to +150c lead temperature range (soldering, 60 sec) 300c junction temperature (t j ) ?65c to +150c operating temperature range ?40c to +85c 1 the op270 inputs are protected by back-to- back diodes. to achieve low noise performance, current-limiting resistors are not used. if the differential voltage exceeds +10 v, the input current should be limited to 25 ma. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
op270 data sheet rev. f | page 6 of 20 typical performance characteristics 00352-004 10 3 4 5 6 7 8 9 2 1 1 10 100 1k voltage noise density (nv/ hz) frequency (hz) t a = 25c v s = 15v 1/f corner = 5hz figure 3. voltage noise density vs. frequency 00352-005 5 3 4 2 1 0 5 10 15 20 voltage noise density (nv/ hz) supply voltage (v) t a = 25c at 1khz at 10khz figure 4. voltage noise density vs. supply voltage 00352-006 noise voltage (100nv/div) time (1 sec/div) 0.1hz to 10hz noise t a = 25c t s = 15v figure 5. 0.1 hz to 10 hz input voltage noise 00352-007 10 1 0.1 10 100 1k 10k current noise density (pa/ hz) frequency (hz) t a = 25c v s = 15v 1/f corner = 200hz figure 6. current noise density vs. frequency 00352-008 40 0 10 20 30 ?30 ?20 ?10 ?75 ?50 ?25 25 50 75 100 125 0 voltage (v) temperature (c) v s = 15v figure 7. input offset voltage vs. temperature 00352-009 5 4 0 1 2 3 02345 1 change in offset voltage (a) time (minutes) t a = 25c v s = 15v figure 8. warm-up offset voltage drift
data sheet op270 rev. f | page 7 of 20 00352-010 7 6 2 3 4 5 input bias current (na) temperature (c) v s = 15v v cm = 0v ?75 ?50 ?25 25 50 75 100 125 0 figure 9. input bias current vs. temperature 00352-011 5 4 0 1 2 3 input offset current (na) temperature (c) v s = 15v v cm = 0v ?75 ?50 ?25 25 50 75 100 125 0 figure 10. input offset current vs. temperature 00352-012 7 6 2 3 4 5 input bias current (na) common-mode voltage (v) ?12.5 ?7.5 ?2.5 2.5 ?10.0 ?5.0 0 5.0 7.5 12.5 10.0 t a = +25c v s = 15v figure 11. input bias current vs. common-mode voltage 00352-013 130 100 110 120 10 20 30 40 50 60 70 80 90 cmr (db) frequency (hz) 1 10 1k 10k 100k 1m 100 t a = 25c v s = 15v figure 12. cmr vs. frequency 00352-014 6 4 5 3 2 0 5 10 15 20 total supply current (ma) supply voltage (v) +125c +25c ?55c figure 13. total supply cu rrent vs. supply voltage 00352-015 8 7 2 1 0 3 4 5 6 total supply current (ma) temperature (c) v s = 15v ?75 ?50 ?25 25 50 75 100 125 0 figure 14. total supply current vs. temperature
op270 data sheet rev. f | page 8 of 20 00352-016 140 100 120 0 20 40 60 80 psr (db) frequency (hz) 1 10 1k 10k 100k 1m 10m 100m 100 t a = 25c ?psr +psr figure 15. psr vs. frequency 00352-017 140 100 120 0 20 40 60 80 open-loop gain (db) frequency (hz) 1 10 1k 10k 100k 1m 10m 100m 100 t a = 25c v s = 15v figure 16. open-loop gain vs. frequency 00352-018 80 60 ?20 0 20 40 closed-loop gain (db) frequency (hz) 1k 10k 100k 1m 10m t a = 25c v s = 15v figure 17. closed-loop gain vs. frequency 00352-019 25 15 20 ?10 ?5 0 5 10 open-loop gain (db) frequency (mhz) 123 4 5 6 7 8 9 1 0 t a = 25c v s = 15v phase shift (degrees) 180 160 140 120 100 80 phase margin = 62 gain phase figure 18. open-loop gain and phase shift vs. frequency 00352-020 5000 1000 2000 3000 4000 0 0 5 10 15 20 25 open-loop gain (v/ma) supply voltage (v) figure 19. open-loop gain vs. supply voltage 00352-021 80 70 40 50 60 phase margin (degrees) temperature (c) ?75 ?50 ?25 25 50 75 100 125 150 0 gain bandwidth product (mhz) 4 5 6 7 8 gbp figure 20. phase margin and gain bandwidth product vs. temperature
data sheet op270 rev. f | page 9 of 20 00352-022 28 20 24 0 4 8 12 16 maximum output swing (v) frequency (hz) 1k 10k 100k 1m 10m t a = 25c v s = 15v thd = 1% figure 21. maximum output swing vs. frequency 00352-023 15 12 13 14 5 6 7 8 9 10 11 maximum output voltage (v) load resistance ( ? ) 100 1k 10k t a = 25c v s = 15v positive swing negative swing figure 22. maximum output voltage vs. load resistance 00352-024 50 40 0 10 20 30 small-signal overshoot (%) capacitive load (pf) 0 200 400 600 800 1000 t a = 25c v s = 15v v in = 100mv a v = +1 figure 23. small-signal overshoot vs. capacitive load 00352-025 100 75 0 25 50 output impedance ( ? ) frequency (hz) 1k 10k 100k 1m 10m t a = 25c v s = 15v a v = 100 a v = 10 a v = 1 figure 24. output im pedance vs. frequency 00352-026 2.2 2.3 2.4 2.5 2.6 2.7 2.8 slew rate (v/s) temperature (c) v s = 15v ?75 ?50 ?25 25 50 75 100 125 0 ?sr +sr figure 25. slew rate vs. temperature 00352-027 190 150 160 170 180 70 80 90 100 110 120 130 140 channel separation (db) frequency (hz) 1 10 1k 10k 100k 1m 100 t a = 25c v s = 15v v o = 20v p-p to 10khz figure 26. channel separation vs. frequency
op270 data sheet rev. f | page 10 of 20 00352-028 0.1 0.01 0.001 10 100 1k 10k total harmonic distortion (%) frequency (hz) t a = 25c v s = 15v v o = 20v p-p r l = 2k ? a v = 10 a v = 1 figure 27. total harmonic distortion vs. frequency 00352-029 t a = 25c v s = 15v a v = +1 r l = 2k ? 5v 20s figure 28. large-signal transient response 00352-030 t a = 25c v s = 15v a v = +1 r l = 2k ? 50mv 200ns figure 29. small-signal transient response
data sheet op270 rev. f | page 11 of 20 test circuits 00325-031 1/2 op270 500 ? 5k ? v 1 20v p-p 1/2 op270 channel separation = 20 log 50 ? 5k ? v 2 v 1 v 2 /1000 figure 30. channel separation test circuit 00325-032 1/2 op270 100k ? 1/2 op270 +18 v ?18v 200k ? 100k ? 2 1 7 3 6 5 4 8 figure 31. burn-in circuit
op270 data sheet rev. f | page 12 of 20 applications information voltage and current noise the op270 is a very low noise dual op amp, exhibiting a typical voltage noise density of only 3.2 nv/hz at 1 khz. because the voltage noise is inversely proportional to the square root of the collector current, the exceptionally low noise characteristic of the op270 is achieved in part by operating the input transistors at high collector currents. current noise, however, is directly proportional to the square root of the collector current. as a result, the outstanding voltage noise density performance of the op270 is gained at the expense of current noise performance, which is normal for low noise amplifiers. to obtain the best noise performance in a circuit, it is vital to understand the relationships among voltage noise (e n ), current noise (i n ), and resistor noise (e t ). total noise and source resistance the total noise of an op amp can be calculated by 2 2 2 )()()( tsn n n eriee ??? where: e n is the total input-referred noise. e n is the op amp voltage noise. i n is the op amp current noise. e t is the source resistance thermal noise. r s is the source resistance. the total noise is referred to the input and at the output is amplified by the circuit gain. figure 32 shows the relationship between total noise at 1 khz and source resistance. when r s is less than 1 k, the total noise is dominated by the voltage noise of the op270 . as r s rises above 1 k, total noise increases and is dominated by resistor noise rather than by the voltage or current noise of the op270 . when r s exceeds 20 k, the current noise of the op270 becomes the major contributor to total noise. 00352-033 100 10 1 100 1k 10k 100k total noise (nv/ hz) source resistance ( ? ) resistor noise only op200 op270 figure 32. total noise vs. source resistance (including resistor noise) at 1 khz figure 33 also shows the relationship between total noise and source resistance, but at 10 hz. total noise increases more quickly than shown in figure 32 because current noise is inversely proportional to the square root of frequency. in figure 33, the current noise of the op270 dominates the total noise when r s is greater than 5 k. figure 32 and figure 33 show that to reduce total noise, source resistance must be kept to a minimum. in applications with a high source resistance, the op200 , with lower current noise than the op270 , can provide lower total noise. 00352-034 100 10 1 100 1k 10k 100k total noise (nv/ hz) source resistance ( ? ) resistor noise only op200 op270 figure 33. total noise vs. source resistance (including resistor noise) at 10 hz figure 34 shows peak-to-peak noise vs. source resistance over the 0.1 hz to 10 hz range. at low values of r s , the voltage noise of the op270 is the major contributor to peak-to-peak noise, with current noise becoming the major contributor as r s increases. the crossover point between the op270 and the op200 for peak-to-peak noise is at a source resistance of 17 k. 00352-035 1k 100 10 100 1k 10k 100k peak-to-peak noise (nv) source resistance ( ? ) resistor noise only op200 op270 figure 34. peak-to-peak noise (0.1 hz to 10 hz) vs. source resistance (including resistor noise)
data sheet op270 rev. f | page 13 of 20 for reference, typical source resistances of some signal sources are listed in table 4. table 4. typical source resistances device source impedance comments strain gage <500 typically used in low frequency applications. magnetic tapehead, microphone <1500 low i b is very important to reduce self-magnetization problems when direct coupling is used. op270 i b can be disregarded. magnetic phonograph cartridge <1500 low i b is important to reduce self-magnetization problems in direct-coupled applications. op270 does not introduce any self-magnetization problems. linear variable differential transformer <1500 used in rugged servo-feedback applications. the bandwidth of interest is 400 hz to 5 khz. 00325-036 op270 dut r1 5 ? r2 5 ? r3 1.24k ? op27e r5 909 ? r4 200 ? r13 5.9k ? r12 10k ? op27e op42e r9 306 ? r10 65.4k ? r11 65.4k ? r8 10k ? c1 2f c4 0.22f d1, d2 1n4148 r6 600 ? c2 0.032f c3 0.22f c5 1f r14 4.99k ? e out gain = 50,000 v s = 15v figure 35. peak-to-peak voltage noise test circuit (0.1 hz to 10 hz)
op270 data sheet rev. f | page 14 of 20 noise measurements peak-to-peak voltage noise the circuit of figure 35 is a test setup for measuring peak-to- peak voltage noise. to measure the 200 nv peak-to-peak noise specification of the op270 in the 0.1 hz to 10 hz range, the following precautions must be observed: ? the device has to be warmed up for at least five minutes. as shown in the warm-up drift curve (see figure 8), the offset voltage typically changes 2 v due to increasing chip temperature after power-up. in the 10 sec measurement interval, these temperature-induced effects can exceed tens of nanovolts. ? for similar reasons, the device has to be well shielded from air currents. shielding also minimizes thermocouple effects. ? sudden motion in the vicinity of the device can also feed through to increase the observed noise. ? the test time to measure noise of 0.1 hz to 10 hz should not exceed 10 sec. as shown in the noise-tester frequency response curve of figure 36, the 0.1 hz corner is defined by only one pole. the test time of 10 sec acts as an additional pole to eliminate noise contribution from the frequency band below 0.1 hz. ? a noise voltage density test is recommended when measuring noise on several units. a 10 hz noise voltage density mea- surement correlates well with a 0.1 hz to 10 hz peak-to-peak noise reading because both results are determined by the white noise and the location of the 1/f corner frequency. ? power should be supplied to the test circuit by well bypassed low noise supplies, such as batteries. such supplies will min- imize output noise introduced via the amplifier supply pins. 00352-037 100 60 80 0 20 40 gain (db) frequency (hz) 0.01 0.1 1 10 100 figure 36. 0.1 hz to 10 hz peak-to-peak voltage noise test circuit frequency response noise measurementnoise voltage density the circuit of figure 37 shows a quick and reliable method for measuring the noise voltage density of dual op amps. the first amplifier is in unity gain, with the final amplifier in a noninverting gain of 101. because the noise voltages of the amplifiers are uncorrelated, they add in rms to yield ? ? ? ? ? ? 2 2 101 nb na out ee e ? ? the op270 is a monolithic device with two identical amplifiers. therefore, the noise voltage densities of the amplifiers match, giving ? ? ? ? 21012101 2 ? ? 00325-038 e out (nv/ hz) 101 ( 2e n ) v s = 15v to spectrum analyzer e out r1 100 ? r2 10k ? 1/2 op270 1/2 op270 figure 37. noise voltage density test circuit noise measurementcurrent noise density the test circuit shown in figure 38 can be used to measure current noise density. the formula relating the voltage output to the current noise density is ?? 2 2 /40 ? ? ? ? ? ? ? ? where: g is a gain of 10,000. r s = 100 k source resistance. 00325-039 op270 dut r1 5 ? r2 100k ? r3 1.24k ? op27e r5 8.06k ? r4 200 ? e nout gain = 10,000 v s = 15v to spectrum analyzer figure 38. current noise density test circuit
data sheet op270 rev. f | page 15 of 20 capacitive load driving and power supply considerations the op270 is unity-gain stable and capable of driving large capacitive loads without oscillating. nonetheless, good supply bypassing is highly recommended. proper supply bypassing reduces problems caused by supply line noise and improves the capacitive load driving capability of the op270 . in the standard feedback amplifier, the output resistance of the op amp combines with the load capacitance to form a low-pass filter that adds phase shift in the feedback network and reduces stability. a simple circuit to eliminate this effect is shown in figure 39. the components c1 and r3 decouple the amplifier from the load capacitance and provide additional stability. the values of c1 and r3 shown in figure 39 are for a load capacitance of up to 1000 pf when used with the op270 . 00325-040 c1 200pf v in v out place supply decoupling capacitor at op270 op270 v + r1 c3 0.1f c2 10f c1 1000pf r2 c4 10f c5 0.1f r3 50 ? + v? + figure 39. driving large capacitive loads unity-gain buffer applications when r f 100 and the input is driven with a fast, large signal pulse (>1 v), the output waveform looks like the one in figure 40. during the fast feedthrough-like portion of the output, the input protection diodes effectively short the output to the input, and a current, limited only by the output short-circuit protection, is drawn by the signal generator. with r f 500 , the output is capable of handling the current requirements (i l 20 ma at 10 v); the amplifier stays in its active mode and a smooth transition occurs. when r f > 3 k, a pole created by r f and the input capacitance (3 pf) of the amplifier creates additional phase shift and reduces phase margin. a small capacitor (20 pf to 50 pf) in parallel with r f helps eliminate this problem. 00325-041 op270 2.4v/s r f figure 40. pulsed operation
op270 data sheet rev. f | page 16 of 20 low phase error amplifier the simple amplifier depicted in figure 41 utilizes a monolithic dual operational amplifier and a few resistors to substantially reduce phase error compared with conventional amplifier designs. at a given gain, the frequency range for a specified phase accuracy is more than a decade greater than that of a standard single op amp amplifier. the low phase error amplifier performs second-order fre- quency compensation through the response of op amp a2 in the feedback loop of a1. both op amps must be extremely well matched in frequency response. at low frequencies, the a1 feedback loop forces v 2 /(k1 + 1) = v in . the a2 feedback loop forces v o /(k1 + 1) = v 2 /(k1 + 1), yielding an overall transfer function of v o /v in = k1 + 1. the dc gain is determined by the resistor divider at the output, v o , and is not directly affected by the resistor divider around a2. note that, like a conventional single op amp amplifier, the dc gain is set by resistor ratios only. minimum gain for the low phase error amplifier is 10. 00325-042 1/2 op270e a2 1/2 op270e a1 r1 v o v 2 v in r1 k1 r2 r2 = r1 t s r2 k2 v o = (k 1 + 1)v in assume a1 and a2 are matched. a o (s) = figure 41. low phase error amplifier figure 42 compares the phase error performance of the low phase error amplifier with a conventional single op amp amplifier and a cascaded two-stage amplifier. the low phase error amplifier shows a much lower phase error, particularly for frequencies where /| t < 0.1. for example, a phase error of ?0.1 occurs at 0.002 /| t for the single op amp amplifier, but at 0.11 /| t for the low phase error amplifier. 00352-043 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 phase shift (degrees) frequency ratio (1/ | )( / t ) 0.001 0.005 0.01 0.1 1 low phase error amplifier cascaded (two stages) single op amp. conventional design 0.05 0.5 figure 42. phase error comparison five-band, low noise, stereo graphic equalizer the graphic equalizer circuit shown in figure 43 provides 15 db of boost or cut over a five-band range. signal-to-noise ratio over a 20 khz bandwidth is better than 100 db and referred to a 3 v rms input. larger inductors can be replaced by active inductors, but consequently reduces the signal-to-noise ratio. 00325-044 1/2 op270e 1/2 op270e r2 3.3k ? r1 47k ? r4 1k ? 60hz tantalum v out v in r14 100 ? r13 3.3k ? c2 6.8f l1 1h c1 0.47f r3 680 ? 200hz r6 1k ? 800hz r8 1k ? 3khz r10 1k ? 10khz r12 1k ? + tantalum c3 1f l2 600mh r5 680 ? + c4 0.22f l3 180mh r7 680 ? + c5 0.047f l4 60mh r9 680 ? + c6 0.022f l5 10mh r11 680 ? + figure 43. five-band, lo w noise graphic equalizer
data sheet op270 rev. f | page 17 of 20 digital panning control figure 44 uses a dac8221 (a dual 12-bit cmos dac) to pan a signal between two channels. one channel is formed by the current output of dac a driving one-half of an op270 in a current-to-voltage converter configuration. the other channel is formed by the complementary output current of dac a, which normally flows to ground through the agnd pin. this complementary current is converted to a voltage by the other half of the op270 , which also holds agnd at virtual ground. gain error due to mismatching between the internal dac ladder resistors and the current-to-voltage feedback resistors is eliminated by using feedback resistors internal to the dac8221. only dac a passes a signal; dac b provides the second feedback resistor. with v ref b unconnected, the current-to- voltage converter, using r fbb , is accurate and not influenced by digital data reaching dac b. distortion of the digital panning control is less than 0.002% over the 20 hz to 20 khz audio range. figure 45 shows the complementary outputs for a 1 khz input signal and a digital ramp applied to the dac data input. dual programmable gain amplifier the du al op270 and the dac8221 (a dual 12-bit cmos dac) can be c ombined to for m a sp ace-saving, du al pro grammable amplifier. t h e digita l code present at th e da c, which is easily set b y a microprocessor, determines th e ratio be tween the i nternal feedback r esistor a nd the r esistance th at the dac ladder p resents to t he op am p feedback loop. gain of e ach amplifier is nv v in o 4096 ?? w here n is the decimal equivalent of the 12-bit digital code present at the dac. if the digital code present at the dac consists of all 0s, the feedback loop opens, causing the op amp output to saturate. a 20 m resistor placed in parallel with the dac feedback loop eliminates this problem with only a very small reduction in gain accuracy. 0 0325-045 1/2 op270gp v in nc r fba 1 1 23 24 22 18 19 cs wr write control 20 6 5 7 3 2 4 3 21 v dd dac8221p 2 8 4 0.01f +15v ?15v out i out a i out b agnd dgnd 5 1/2 op270gp dac b dac a +5v 10f ? + 10f ? + 0.1f r fbb v ref a v ref b dac a/dac b dac data bus pins 6 (msb) to 17 (lsb) out figure 44. digital panning control 00352-046 5v 5v 1ms a out a out figure 45. digital panning control output
op270 data sheet rev. f | page 18 of 20 00325-047 v in b 1 19 18 write control 20 6 5 7 3 23 21 v dd dac8221p 2 8 4 dgnd 5 1/2 op270gp 1/2 op270ez dac b dac a +5v 0.01f +15 v 10f ? + ?15v 10f ? + 0.1f 24 22 1 i out b 2 i out a agnd v ref b 4 v ref a v out b v out a 20m ? 20m ? dac data bus pins 6 (msb) to 17 (lsb) r fbb v in a 3 r fba figure 46. dual programmable gain amplifier bias 00325-003 v? ? in v + out +in figure 47. simplified schematic (one of two amplifiers is shown)
data sheet op270 rev. f | page 19 of 20 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.055 (1.40) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 14 5 8 figure 48. 8-lead ceramic dual in-line package [cerdip] z-suffix (q-8) dimensions shown in inches and (millimeters) compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 49. 8-lead plastic dual in-line package [pdip] narrow body p-suffix (n-8) dimensions shown in inches and (millimeters)
op270 data sheet rev. f | page 20 of 20 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 50. 16-lead standard small outline package [soic_w] wide body s-suffix (rw-16) dimensions shown in millimeters and (inches) ordering guide model 1 t a = +25c v os max (v) jc (c/w) ja 2 (c/w) temperature range package description package option op270ez 75 12 134 ?40c to +85c 8-lead cerdip q-8 (z-suffix) op270fz 150 12 134 ?40c to +85c 8-lead cerdip q-8 (z-suffix) op270gp 250 37 96 ?40c to +85c 8-lead pdip n-8 (p-suffix) op270gpz ?40c to +85c 8-lead pdip n-8 (p-suffix) op270gs 250 27 92 ?40c to +85c 16-lead soic_w rw-16 (s-suffix) op270gs-reel ?40c to +85c 16-lead soic_w rw-16 (s-suffix) op270gsz ?40c to +85c 16-lead soic_w rw-16 (s-suffix) OP270GSZ-REEL ?40c to +85c 16-lead soic_w rw-16 (s-suffix) 1 the op270gpz, op270gsz, and op270gsz-r eel are rohs compliant parts. 2 ja is specified for worst-case mounting conditions, that is, ja is specified for device in sock et for cerdip and pdip packages; ja is specified for device soldered to printed circuit board for soic package. ?2001C2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00325-0-10/15(f)

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